Integrated circuits are commonly used to make a wide variety of electronic devices, such as memory chips. One aim in production is to reduce the size of integrated circuits, so as to increase the density of the individual components and consequently enhance the functionality of an integrated circuit. The minimum pitch on an integrated circuit (the minimum distance between the same points of two adjacent structures of the same type, e.g., two adjacent gate conductors) is often used as a representative measure of the circuit's density. Increases in circuit density often are limited by the resolution of the available photolithographic equipment. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is related to its resolution capability.
Some attempts have been made to try to reduce the pitch of an integrated circuit device below that of the minimum pitch produced lithographically. Generally, multiple exposure and multiple patterning schemes have been used to achieve pitch reduction in semiconductor structures. However, lithographic methods based on multiple exposure and patterning schemes require using complicated multiple layer stacks, and require numerous exposure and etching steps. For example, for the litho-etch-litho-etch (LELE) double patterning process, complicated tri-layer lithographic stack is used. The exposure, etching, re-exposure, and re-etching steps in the LELE scheme produce critical dimension bias and significantly increase the chance for creating defects. In sum, the conventional method of using multiple exposure and patterning schemes to reduce pitch in a semiconductor device are difficult to control and show varying results. It is therefore necessary to provide a simpler, and more reliable method that can reduce the pitch in a semiconductor device.